The ever-expanding network infrastructure of Internet-of-everything (IoE) significantly increases the social productivity and facilitates our daily life. Advanced microelectronic chips are the cornerstone to keep trillions of devices always online efficiently. Besides the low-power and low-cost requirements, these chips are also expected to be self-powered to alleviate the battery replacement effort. Moreover, the off-chip components should be avoided to enable a tiny device that can be flexibly deployed. This project succeeded in inventing a wide variety of circuit techniques for advanced IoE chips, for examples, the saw-less wireless transmitter chip for 5G new radio; the energy-harvesting interface chip that can support ultra-wide input and output voltage range; high-performance oscillator chips that can fulfill the requirements of different applications below 70GHz.

The techniques and IC prototypes developed from this project were transferred via 30 academic publications and 2 authorized US patents, including 9 papers in the IEEE Journal of Solid-State Circuits (JSSC) and 5 papers in the IEEE International Solid-State Circuits Conference (ISSCC), which are The Topmost IC journal and conference in the IC area. This publication record shows the leading position of our group among others in the world-class universities in the same period. Besides, this project trained a number of highly-caliber Ph.D. students who joined the top IC companies or universities after graduation. Meanwhile, we are conducting collaboration projects with IC companies from the Greater Bay Area to transfer the developed techniques from this project to the industry.

Fig 1 Chip photos from our 14 ISSCC/JSSC papers for enabling IoE connectivity.

Fig 2 The schematic (left) and chip photo (right) of our developed saw-less wireless transmitter chip for 5G new radio. Benchmarked with state-of-the-art solutions, the proposed bandwidth-extended N-path filter technique can simultaneously suppress the out-of-band noise, improve the output power and transmitter efficiency as well as reduce the chip area.

Fig 3 The testing environment of our developed energy-harvesting interface chip that can support ultra-wide input and output voltage range (left). Benchmarked with state-of-the-art solutions in bulk CMOS, our design breaks the tradeoff between the peak efficiency and the power density (right).